Здравствуйте,недавно начал изучать язык vhdl,но никак не могу понять  свои ошибки в синтаксисе. По заданию,нужно было реализовать таймер.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cnt128 is
    Port ( c : in  STD_LOGIC;
           q : out  STD_LOGIC_VECTOR (6 downto 0);
           timer : out  STD_LOGIC);
end cnt128;

architecture Behavioral of cnt128 is
signal s:std_logic_vector (6 downto 0);="0000000";
constant const128:std_logic_vector (6 downto 0);="1111111";

begin
process ©
begin
if rising_edge© then
if (s="1111111") then s="0000000" 
else
s<=s+1;
end if
end process;
q<=s;
process (s)
begin
if const128=s then timer<='1' else timer <='0'
end if
end process
end Behavioral;