Вот, пример. Можно "перевести" на Делфи:| Код |
/*
* PROCESSOR_REGISTERS
*/
typedef struct _ProcessorRegisters {
DWORD EAX;
DWORD EBX;
DWORD ECX;
DWORD EDX;
} PROCESSOR_REGISTERS;
/*
* CPU_CACHE_STRUCT
*/
typedef struct _stL1Cache {
DWORD Size;
DWORD Associativity;
DWORD LineSize;
} CPU_CACHE_STRUCT;
/*
* CPU_L1_CACHE
*/
typedef struct _L1Cache {
CPU_CACHE_STRUCT Data;
CPU_CACHE_STRUCT Instruction;
} CPU_L1_CACHE;
/*
* CPU_CACHE
*/
typedef struct _Cache {
CPU_L1_CACHE L1;
CPU_CACHE_STRUCT L2;
CPU_CACHE_STRUCT L3;
} CPU_CACHE;
void cCPUDetect::GetAmdCache(CPU_CACHE& Cahe)
{
PROCESSOR_REGISTERS Registers;
_asm
{
mov eax,0x80000005
CPU_ID
mov Registers.EAX, eax
mov Registers.EBX, ebx
mov Registers.ECX, ecx
mov Registers.EDX, edx
}
Cahe.L1.Data.LineSize = Registers.ECX & 0x000000FF;
Cahe.L1.Data.Associativity = ( Registers.ECX & 0x00FF0000 ) >> 16;
Cahe.L1.Data.Size = ( Registers.ECX & 0xFF000000 ) >> 24;
if ( Cahe.L1.Data.Associativity == 6 ) Cahe.L1.Data.Associativity=8;
if ( Cahe.L1.Data.Associativity == 8 ) Cahe.L1.Data.Associativity=16;
Cahe.L1.Instruction.LineSize = Registers.EDX & 0x000000FF;
Cahe.L1.Instruction.Associativity = ( Registers.EDX & 0x00FF0000 ) >> 16;
Cahe.L1.Instruction.Size = ( Registers.EDX & 0xFF000000 ) >> 24;
if ( Cahe.L1.Instruction.Associativity == 6 ) Cahe.L1.Instruction.Associativity=8;
if ( Cahe.L1.Instruction.Associativity == 8 ) Cahe.L1.Instruction.Associativity=16;
_asm
{
mov eax,0x80000006
CPU_ID
mov Registers.EAX, eax
mov Registers.EBX, ebx
mov Registers.ECX, ecx
mov Registers.EDX, edx
}
Cahe.L2.LineSize = Registers.ECX & 0x000000FF;
Cahe.L2.Associativity = ( Registers.ECX & 0x0000FF00 ) >> 12;
Cahe.L2.Size = ( Registers.ECX & 0xFFFF0000 ) >> 16;
if (Cahe.L2.Associativity==6) Cahe.L2.Associativity=8;
if (Cahe.L2.Associativity==8) Cahe.L2.Associativity=16;
}
void cCPUDetect::GetIntelCache(CPU_CACHE& Cahe)
{
PROCESSOR_REGISTERS Registers;
memset(&Cahe,0,sizeof(Cahe));
_asm
{
mov eax,0x00000002
CPU_ID
mov Registers.EAX, eax
mov Registers.EBX, ebx
mov Registers.ECX, ecx
mov Registers.EDX, edx
}
BYTE* part = (BYTE*)&Registers;
size_t count = 0;
while (count<16) {
++count;
switch( *(part+count) ) {
case 0x06:
Cahe.L1.Instruction.Size = 8;
Cahe.L1.Instruction.Associativity = 4;
Cahe.L1.Instruction.LineSize = 32;
break;
case 0x08:
Cahe.L1.Instruction.Size = 16;
Cahe.L1.Instruction.Associativity = 4;
Cahe.L1.Instruction.LineSize = 32;
break;
case 0x0A:
Cahe.L1.Data.Size = 8;
Cahe.L1.Data.Associativity = 2;
Cahe.L1.Data.LineSize = 32;
break;
case 0x0C:
Cahe.L1.Data.Size = 16;
Cahe.L1.Data.Associativity = 4;
Cahe.L1.Data.LineSize = 32;
break;
case 0x22:
Cahe.L3.Size = 512;
Cahe.L3.Associativity = 4;
Cahe.L3.LineSize = 64;
break;
case 0x23:
Cahe.L3.Size = 1024;
Cahe.L3.Associativity = 8;
Cahe.L3.LineSize = 64;
break;
case 0x25:
Cahe.L3.Size = 2*1024;
Cahe.L3.Associativity = 8;
Cahe.L3.LineSize = 64;
break;
case 0x29:
Cahe.L3.Size = 4*1024;
Cahe.L3.Associativity = 8;
Cahe.L3.LineSize = 64;
break;
case 0x2C:
Cahe.L1.Data.Size = 32;
Cahe.L1.Data.Associativity = 8;
Cahe.L1.Data.LineSize = 64;
break;
case 0x30:
Cahe.L1.Instruction.Size = 32;
Cahe.L1.Instruction.Associativity = 8;
Cahe.L1.Instruction.LineSize = 64;
break;
case 0x39:
Cahe.L2.Size = 128;
Cahe.L2.Associativity = 4;
Cahe.L2.LineSize = 64;
break;
case 0x3B:
Cahe.L2.Size = 128;
Cahe.L2.Associativity = 2;
Cahe.L2.LineSize = 64;
break;
case 0x3C:
Cahe.L2.Size = 256;
Cahe.L2.Associativity = 4;
Cahe.L2.LineSize = 64;
break;
/*case 0x40:
break;*/
case 0x41:
Cahe.L2.Size = 128;
Cahe.L2.Associativity = 4;
Cahe.L2.LineSize = 32;
break;
case 0x42:
Cahe.L2.Size = 256;
Cahe.L2.Associativity = 4;
Cahe.L2.LineSize = 32;
break;
case 0x43:
Cahe.L2.Size = 512;
Cahe.L2.Associativity = 4;
Cahe.L2.LineSize = 32;
break;
case 0x44:
Cahe.L2.Size = 1024;
Cahe.L2.Associativity = 4;
Cahe.L2.LineSize = 32;
break;
case 0x60:
Cahe.L1.Data.Size = 16;
Cahe.L1.Data.Associativity = 8;
Cahe.L1.Data.LineSize = 64;
break;
case 0x66:
Cahe.L1.Data.Size = 8;
Cahe.L1.Data.Associativity = 4;
Cahe.L1.Data.LineSize = 64;
break;
case 0x67:
Cahe.L1.Data.Size = 16;
Cahe.L1.Data.Associativity = 4;
Cahe.L1.Data.LineSize = 64;
break;
case 0x68:
Cahe.L1.Data.Size = 32;
Cahe.L1.Data.Associativity = 4;
Cahe.L1.Data.LineSize = 64;
break;
case 0x78:
Cahe.L2.Size = 1024;
Cahe.L2.Associativity = 4;
Cahe.L2.LineSize = 64;
break;
case 0x79:
Cahe.L2.Size = 128;
Cahe.L2.Associativity = 8;
Cahe.L2.LineSize = 64;
break;
case 0x7A:
Cahe.L2.Size = 256;
Cahe.L2.Associativity = 8;
Cahe.L2.LineSize = 64;
break;
case 0x7B:
Cahe.L2.Size = 512;
Cahe.L2.Associativity = 8;
Cahe.L2.LineSize = 64;
break;
case 0x7C:
Cahe.L2.Size = 1024;
Cahe.L2.Associativity = 8;
Cahe.L2.LineSize = 64;
break;
case 0x7D:
Cahe.L2.Size = 2*1024;
Cahe.L2.Associativity = 8;
Cahe.L2.LineSize = 64;
break;
case 0x7F:
Cahe.L2.Size = 512;
Cahe.L2.Associativity = 2;
Cahe.L2.LineSize = 64;
break;
case 0x82:
Cahe.L2.Size = 256;
Cahe.L2.Associativity = 8;
Cahe.L2.LineSize = 32;
break;
case 0x83:
Cahe.L2.Size = 512;
Cahe.L2.Associativity = 8;
Cahe.L2.LineSize = 32;
break;
case 0x84:
Cahe.L2.Size = 1024;
Cahe.L2.Associativity = 8;
Cahe.L2.LineSize = 32;
break;
case 0x85:
Cahe.L2.Size = 2*1024;
Cahe.L2.Associativity = 8;
Cahe.L2.LineSize = 32;
break;
case 0x86:
Cahe.L2.Size = 512;
Cahe.L2.Associativity = 4;
Cahe.L2.LineSize = 64;
break;
case 0x87:
Cahe.L2.Size = 1024;
Cahe.L2.Associativity = 8;
Cahe.L2.LineSize = 64;
break;
default:
break;
}
}
} |
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