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/****************************************************************************
** - iotiny26.h -
**
** This file declares the internal register addresses for ATtiny26.
**
** Used with iccAVR and aAVR.
**
** Copyright IAR Systems 2002. All rights reserved.
**
** File version: $Revision: 1.3 $
**
***************************************************************************/
#include "iomacro.h"
#if TID_GUARD(0)
#error This file should only be compiled with iccavr or aavr whith processor option -v0
#endif /* TID_GUARD(0) */
/* Include the SFR part if this file has not been included before,
* OR this file is included by the assembler (SFRs must be defined in
* each assembler module). */
#if !defined(__IOTINY26_H) || defined(__IAR_SYSTEMS_ASM__)
#pragma language=extended
/*==========================*/
/* Predefined SFR Addresses */
/*==========================*/
/****************************************************************************
* An example showing the SFR_B() macro call,
* the expanded result and usage of this result:
*
* SFR_B(AVR, 0x1F) Expands to:
* __io union {
* unsigned char AVR; // The sfrb as 1 byte
* struct { // The sfrb as 8 bits
* unsigned char AVR_Bit0:1,
* AVR_Bit1:1,
* AVR_Bit2:1,
* AVR_Bit3:1,
* AVR_Bit4:1,
* AVR_Bit5:1,
* AVR_Bit6:1,
* AVR_Bit7:1;
* };
* } @ 0x1F;
* Examples of how to use the expanded result:
* AVR |= (1<<5);
* or like this:
* AVR_Bit5 = 1;
***************************************************************************/
SFR_W(ADC, 0x04) /* ADC Data Register */
SFR_B(ADCSR, 0x06) /* ADC Control and Status Register */
SFR_B(ADMUX, 0x07) /* ADC Multiplexer Select Register */
SFR_B(ACSR, 0x08) /* Analog Comparator Control and Status Register */
SFR_B(USICR, 0x0D) /* Universal Serial Interface Control Register */
SFR_B(USISR, 0x0E) /* Universal Serial Interface Status Register */
SFR_B(USIDR, 0x0F) /* Universal Serial Interface Data Register */
SFR_B(PINB, 0x16) /* Input Pins, Port B */
SFR_B(DDRB, 0x17) /* Data Direction Register, Port B */
SFR_B(PORTB, 0x18) /* Data Register, Port B */
SFR_B(PINA, 0x19) /* Input Pins, Port A */
SFR_B(DDRA, 0x1A) /* Data Direction Register, Port A */
SFR_B(PORTA, 0x1B) /* Data Register, Port A */
SFR_B(EECR, 0x1C) /* EEPROM Control Register */
SFR_B(EEDR, 0x1D) /* EEPROM Data Register */
SFR_B(EEAR, 0x1E) /* EEPROM Address Register */
SFR_B(WDTCR, 0x21) /* Watchdog Timer Control Register */
SFR_B(PLLCSR, 0x29) /* PLL Control and Status Register */
SFR_B(OCR1C, 0x2B) /* Timer/Counter1 Output Compare Register C */
SFR_B(OCR1B, 0x2C) /* Timer/Counter1 Output Compare Register B */
SFR_B(OCR1A, 0x2D) /* Timer/Counter1 Output Compare Register A */
SFR_B(TCNT1, 0x2E) /* Timer/Counter1 */
SFR_B(TCCR1B, 0x2F) /* Timer/Counter1 Control Register B */
SFR_B(TCCR1A, 0x30) /* Timer/Counter1 Control Register A */
SFR_B(OSCCAL, 0x31) /* Oscillator Calibration Register */
SFR_B(TCNT0, 0x32) /* Timer/Counter0 */
SFR_B(TCCR0, 0x33) /* Timer/Counter0 Control Register */
SFR_B(MCUSR, 0x34) /* MCU Status Register */
SFR_B(MCUCR, 0x35) /* MCU Control Register */
SFR_B(TIFR, 0x38) /* Timer/Counter Interrupt Flag Register */
SFR_B(TIMSK, 0x39) /* Timer/Counter Interrupt Mask Register */
SFR_B(GIFR, 0x3A) /* General Interrupt Flag Register */
SFR_B(GIMSK, 0x3B) /* General Interrupt Mask Register */
SFR_B(SP, 0x3D) /* Stack Pointer */
SFR_B(SREG, 0x3F) /* Status Register */
#ifndef __IOTINY26_H
#define __IOTINY26_H
/* SFRs are local in assembler modules (so this file may need to be */
/* included in more than one module in the same source file), */
/* but #defines must only be made once per source file. */
/*==============================*/
/* Interrupt Vector Definitions */
/*==============================*/
/* NB! vectors are specified as byte addresses */
#define RESET_vect (0x00)
#define INT0_vect (0x02)
#define IO_PINS_vect (0x04)
#define TIMER1_CMPA_vect (0x06)
#define TIMER1_CMPB_vect (0x08)
#define TIMER1_OVF1_vect (0x0A)
#define TIMER0_OVF0_vect (0x0C)
#define USI_STRT_vect (0x0E)
#define USI_OVF_vect (0x10)
#define EE_RDY_vect (0x12)
#define ANA_COMP_vect (0x14)
#define ADC_vect (0x16)
#ifdef __IAR_SYSTEMS_ASM__
#ifndef ENABLE_BIT_DEFINITIONS
#define ENABLE_BIT_DEFINITIONS
#endif /* ENABLE_BIT_DEFINITIONS */
#endif /* __IAR_SYSTEMS_ASM__ */
#ifdef ENABLE_BIT_DEFINITIONS
/* Bit definitions for use with the IAR Assembler
The Register Bit names are represented by their bit number (0-7). */
/* ADC Control and Status Register - ADCSR */
#define ADEN 7
#define ADSC 6
#define ADFR 5
#define ADIF 4
#define ADIE 3
#define ADPS2 2
#define ADPS1 1
#define ADPS0 0
/* ADC Multiplexer Selection Register - ADMUX */
#define REFS1 7
#define REFS0 6
#define ADLAR 5
#define MUX4 4
#define MUX3 3
#define MUX2 2
#define MUX1 1
#define MUX0 0
/* Analog Comparator Control And Status Register - ACSR */
#define ACD 7
#define ACBG 6
#define ACO 5
#define ACI 4
#define ACIE 3
#define ACME 2
#define ACIS1 1
#define ACIS0 0
/* USI Control Register - USICR */
#define USISIE 7
#define USIOIE 6
#define USIWM1 5
#define USIWM0 4
#define USICS1 3
#define USICS0 2
#define USICLK 1
#define USITC 0
/* USI Status Register - USISR */
#define USISIF 7
#define USIOIF 6
#define USIPF 5
#define USIDC 4
#define USICNT3 3
#define USICNT2 2
#define USICNT1 1
#define USICNT0 0
/* Port B Input Pins Address - PINB */
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
/* Port B Data Direction Register - DDRB */
#define DDB7 7
#define DDB6 6
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
/* Port B Data Register - PORTB */
#define PB7 7
#define PB6 6
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
/* Port B Data Register - PORTB */
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
/* Port A Input Pins Address - PINA */
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0
/* Port A Data Direction Register - DDRA */
#define DDA7 7
#define DDA6 6
#define DDA5 5
#define DDA4 4
#define DDA3 3
#define DDA2 2
#define DDA1 1
#define DDA0 0
/* Port A Data Register - PORTA */
#define PA7 7
#define PA6 6
#define PA5 5
#define PA4 4
#define PA3 3
#define PA2 2
#define PA1 1
#define PA0 0
/* Port A Data Register - PORTA */
#define PORTA7 7
#define PORTA6 6
#define PORTA5 5
#define PORTA4 4
#define PORTA3 3
#define PORTA2 2
#define PORTA1 1
#define PORTA0 0
/* EEPROM Control Register - EECR */
#define EERIE 3
#define EEMWE 2
#define EEWE 1
#define EERE 0
/* EEPROM Address Register - EEAR */
#define EEAR6 6
#define EEAR5 5
#define EEAR4 4
#define EEAR3 3
#define EEAR2 2
#define EEAR1 1
#define EEAR0 0
/* Watchdog Timer Control Register - WDTCR */
#define WDCE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/* PLL Control and Status Register - PLLCSR */
#define PCKE 2
#define PLLE 1
#define PLOCK 0
/* Timer/Counter1 Control Register B - TCCR1B */
#define CTC1 7
#define PSR1 6
#define CS13 3
#define CS12 2
#define CS11 1
#define CS10 0
/* Timer/Counter1 Control Register A - TCCR1A */
#define COM1A1 7
#define COM1A0 6
#define COM1B1 5
#define COM1B0 4
#define FOC1A 3
#define FOC1B 2
#define PWM1A 1
#define PWM1B 0
/* Timer/Counter0 Control Register - TCCR0 */
#define PSR0 3
#define CS02 2
#define CS01 1
#define CS00 0
/* MCU Status Register - MCUSR */
#define WDRF 3
#define BORF 2
#define EXTRF 1
#define PORF 0
/* MCU Control Register - MCUCR */
#define PUD 6
#define SE 5
#define SM1 4
#define SM0 3
#define ISC01 1
#define ISC00 0
/* Timer/Counter Interrupt Flag Register - TIFR */
#define OCF1A 6
#define OCF1B 5
#define TOV1 2
#define TOV0 1
/* Timer/Counter Interrupt Mask register - TIMSK */
#define OCIE1A 6
#define OCIE1B 5
#define TOIE1 2
#define TOIE0 1
/* General Interrupt Flag Register - GIFR */
#define INTF0 6
#define PCIF 5
/* General Interrupt Mask register - GIMSK */
#define INT0 6
#define PCIE1 5
#define PCIE0 4
/* Stack Pointer - SP */
#define SP7 7
#define SP6 6
#define SP5 5
#define SP4 4
#define SP3 3
#define SP2 2
#define SP1 1
#define SP0 0
/* Pointer definition */
#define XL R26
#define XH R27
#define YL R28
#define YH R29
#define ZL R30
#define ZH R31
/* Contants */
#define RAMEND 0xDF /* Last On-Chip SRAM Location */
#define XRAMEND 0xDF
#define E2END 0x7F
#define FLASHEND 0x07FF
#endif /* ENABLE_BIT_DEFINITIONS */
#endif /* __IOTINY26_H (define part) */
#pragma language=default
#endif /* __IOTINY26_H (SFR part) */
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