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Задание:
Построить модель на VHDL и промоделировать в ModelSim делитель частоты с коэффициентом деления 61 с использованием счетчиков ИЕ17
вот написала код на vhdl
а он некорректно работает. ну на выход должно выдаваться 1 через период кратный 61 (ну если правильно понимаю), а там всегда 0. не могу найти ошибку. помогите пожалуйста исправить:http://s2.ipicture.ru/uploads/20130607/RGKdvM1w.jpg| Код |
--Generator--
entity Generator is
port(c: out bit);
end Generator;
architecture Generator of Generator is
constant length : time := 100 ns;
begin
process begin
for i in 1 to 400 loop
c <= '0';
wait for length;
c <= '1';
wait for length;
end loop;
end process;
end Generator;
--IE17--
entity Counter is
port (P, D1, D2, D4, D8, ECR, ECT, C, EWR, UD: in bit; Q1, Q2, Q4, Q8, CR: out bit);
end Counter;
architecture Counter of Counter is
constant delay : time:= 40 ns;
Begin
process(ECR, ECT, EWR, UD, C, P)
Variable count, divide : INTEGER;
begin
if P'event and P = '1' then
count := 0;
Q1 <= '0';
Q2 <= '0';
Q4 <= '0';
Q8 <= '0';
CR <= '0';
end if;
if P = '1' then
if EWR = '0' then
Q1 <= D1 after delay;
Q2 <= D2 after delay;
Q4 <= D4 after delay;
Q8 <= D8 after delay;
else
if C'event and C = '1' and ECR = '0' and ECT = '0' then --plus 1--
count := count + 1;
end if;
if UD'event and UD = '0' and ECR = '0' and ECT = '0' then --minus 1--
count := count - 1;
end if;
if count = 15 then
CR <= '1' after delay;
end if;
if count <= 15 and count >= 0 then
CR <= '0' after delay;
if count mod 2 = 1 then
Q1 <= '1' after delay;
else
Q1 <= '0' after delay;
end if;
divide := count / 2;
if divide mod 2 = 1 then
Q2 <= '1' after delay;
else
Q2 <= '0' after delay;
end if;
divide := divide / 2;
if divide mod 2 = 1 then
Q4 <= '1' after delay;
else
Q4 <= '0' after delay;
end if;
divide := divide / 2;
if divide mod 2 = 1 then
Q8 <= '1' after delay;
else
Q8 <= '0' after delay;
end if;
end if;
end if;
end if;
end process;
end Counter;
--AND--
entity KON is
port(b0, b1, b2, b3, b4, b5, b6, b7: in bit; a: out bit);
end KON;
architecture KON of KON is begin
process (b0,b1,b2,b3,b4,b5,b6,b7) begin
if b0='1' and b1='1' and b2='1' and b3='1' and b4 = '1' and b5 = '1' and b6 = '1' and b7 = '1' then
a<='1' after 10 ns;
else
a<='0' after 10 ns;
end if;
end process;
end KON;
--element OR--
entity DIZ is
port (I1, I2: in bit; O: out bit);
end DIZ;
architecture DIZ of DIZ is begin
process (I1, I2) begin
O <= I1 or I2 after 10 ns;
end process;
end DIZ;
--NOT--
entity Invertor is
port (I: in bit; O: out bit);
end invertor;
architecture Invertor of Invertor is begin
process (I) begin
O <= not I after 10 ns;
end process;
end Invertor;
--Automat--
entity Auto is
port (I: in bit; O: out bit);
end Auto;
architecture Auto of Auto is
component Counter
port (P, D1, D2, D4, D8, ECR, ECT, C, EWR, UD: in bit; Q1, Q2, Q4, Q8, CR: out bit);
end component;
component Invertor
port (I: in bit; O: out bit);
end component;
component KON
port(b0,b1,b2,b3, b4, b5, b6, b7: in bit; a: out bit);
end component;
component DIZ
port (I1, I2: in bit; O: out bit);
end component;
signal P, D1, D2, D4, D8, ECR1, ECR2, ECT1, C, EWR1, EWR2, UD,
Q11, Q21, Q41, Q81, Q12, Q22, Q42, Q82,
notQ21, notQ41, notQ81, notQ12, notQ22, notQ82,
CR1, CR2, A, notA: bit;
Begin
D1 <= '0';
D2 <= '0';
D4 <= '0';
D8 <= '0';
-- EWR1 <= '1';--
-- EWR2 <= '1';--
-- UD <= '1';--
ECR1 <= '0';
ECR2 <= '0';
ECT1 <= '0';
Count1: Counter
port map (P, D1, D2, D4, D8, ECR1, ECT1, I, EWR1, notA, Q11, Q21, Q41, Q81, CR1);
Count2: Counter
port map (P, D1, D2, D4, D8, ECR2, CR1, I, EWR2, notA, Q12, Q22, Q42, Q82, CR2);
DZ1: DIZ
port map (CR1, notA, EWR1);
DZ2: DIZ
port map (CR2, notA, EWR2);
INV1: Invertor
port map (Q21, notQ21);
INV2: Invertor
port map (Q41, notQ41);
INV3: Invertor
port map (Q81, notQ81);
INV4: Invertor
port map (Q12, notQ12);
INV5: Invertor
port map (Q22, notQ22);
INV6: Invertor
port map (Q82, notQ82);
K: KON
port map (Q11, notQ21, notQ41, notQ81, notQ12, notQ22, Q42, notQ82, A); --find 61--
-- INV7: Invertor
-- port map (A, notA);
O <= A;
process (P) begin
P <= '0';
P <= '1' after 5 ns;
end process;
enD Auto;
--discription of all circuit--
entity circuit is
end circuit;
architecture Circuit of circuit is
component Generator
port (C: out bit);
end component;
component Auto
port(I: in bit; O: out bit);
end component;
signal I, O: bit;
begin
G: generator
port map (I);
Au: Auto
port map (I, O);
end Circuit;
--TEST--
entity TEST_Auto is
end TEST_Auto;
architecture TEST_Auto of TEST_Auto is
component Auto
port (I: in bit; O: out bit);
end component;
component generator
port (C: out bit);
end component;
signal test_c, test_p, test_o: bit;
begin
G: Generator
port map (test_c);
A: Auto
port map (test_c, test_o);
end TEST_Auto;
entity TEST is
end TEST;
architecture TEST of TEST is
component Circuit
end component;
begin
C: Circuit;
end TEST;
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делитель с использованием счётчика ие17 на vhdl 
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